4 bit synchronous counter lab manual

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4 bit synchronous counter lab manual

The prescribed sequence can be a binary sequence or any other sequence. A counter that goes through 2 N (N is the number of flip-flops in the series)The modulus of a counter is the number of different states it is allowed to have. Counter modulus is normally 2 N unless controlled by a feedback circuit which limits the number of possible states (an example being the decimal counter). Counters are very widely used in almost all computers and other digital electronic systems. There are two major categories of counters: asynchronous counters and synchronous counters. In other words, in asynchronous counters, the CLK inputs of all flip-flops (except the first one) are triggered not by the incoming pulses but rather by the transition that occurs in other flip-flops. Therefore, the change of state of a particular flip-flop is dependent upon the present state of other flip-flops. Fig. 1 shows a count-up ripple counter. When a transition from, say, 0111 to 1000 occurs, the one-to-zero transition of the low-order three bits ripples from bit to bit. Since each flip-flop has a non-zero propagation delay, ripple counters are relatively slow. Therefore, an upper limit on the number of flip-flops in the flip-flop chain ought to be imposed. Each flip-flop is clocked by the same clock signal. Each gate selectively controls when each more significant bit flip-flop is to change state (toggle) on the next clock transition. Such control (enable) can be realized by setting, for example, the J and K inputs of a J-K flip-flop. Because of this control, the addition of a common clock will synchronize data transfer and all flip-flops will change state simultaneously. The important feature of a synchronous counter is that the transitions of the individual flip-flops are synchronized to a master clock signal. There are two basic schemes for generating the J and K inputs. One of them is illustrated in the four-bit binary counter shown in Fig. 2.

Notice that the information to the J-K inputs is formed in a parallel fashion. The counter is accordingly termed as synchronous parallel counter. In the parallel scheme the number of inputs to each AND gate increases linearly with the number of stages. For this added expense one gets the fastest possible synchronous counting circuit. Although the serial scheme is slower than the parallel scheme, the number of inputs to the AND gate per stage is constant in the serial case (two inputs per stage). Now connect CLK to a pulse generator in your pencil box (J-K flip-flops in 74LS76 are negative edge triggered) and start counting by pushing the pulser button. Continue the process and record the output of each transition in a truth table. Does it count correctly? Make the modification and tryFrom the transition. It also useful other students who are pursuing course on Digital design. Download full-text PDF Codes are of different types. The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes t he two systems compatible even though each uses different binary code. Gray Code is one of t he most important codes. It is a non-weighted code which belongs to a class of codes called minimum change codes. In this codes while traversing from one step to another step, only one bit in the The input variable are designated as B3, B2, B1, B0 and the output variables are designated as G3, G2, G1, G0. From the truth table, combinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. A two-level logic diagram may be obtained directly from the Boolean expressions derived by the k - map.RESULT: Thus the code convertors circuits were designed using logic gates and their truth table were verified.

APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. IC IC 7483 1 2. EX-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - 40 THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The carries are connected in chain through the full adder. The mode input M controls the operation.Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. An BCD adder that adds 2 BCD digits and produce a sum digit in BCD format. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum.RESULT: Thus the 4 bit binary adder, 4 bit binary subtractor and BCD adder were designed using logic gates and their truth table was verified. VIVA QUESTIONS 1. Distinguish between Full Adder, 4 bit Binary adder 2. What is BCD? 3. How many pins are there in Ic 7483? 4. What is the need of Binary adder? 5. What is a Carry Look ahead Adder? 6. Is IC 7483 can be used for Adders and Subtractors? How? 7. Give the difference between a Half adder and a Parallel adder 8. How multipliers are utilized using adders 9. What is 4 bit subtraction? 10. Compare BCD adder, Binary adder EXP NO.: DATE: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2 n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line. RESULT: Thus the multiplexer and de-multiplexer circuit was designed using logic gates and their truth table was verified.An encoder has 2 n input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding bi nary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. I t has an ambiguila that when all inputs are zero the outputs are zero. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e., there is one to one mapping can be expressed in truth table.Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation.

RESULT: Thus the 4 bit ripple counter (Modulus 16), mod -10 ripple counter and mod- 12 ripple counter circuits were designed using JK flip-flops and their output was verified. APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. JK FLIP FLOP IC 7476 2 In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the i nput pulses. Thus, all the flip- flops change state simultaneously (in parallel).RESULT: Thus Up counter and Down counter was designed successfully using IC 7476 and its truth table was verified successfully. VIVA QUESTIONS 1. Compare Synchronous, Asynchronous counters? 2. What is State diagram? 3. What is the disadvantage of Synchronous counter? 4. How will you design a synchronous counter? 5. What are the types of Flip-flops? EXP NO.: DATE: The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right. PIN DIAGRAM: IC7474 Dual D Flip-flop with Preset and Clear RESULT: Thus the various shift registers were designed successfully using flip- flops and their truth tables were verified successfully. VIVA QUESTIONS 1. What is a Register? 2. What is a Shift Register? 3. What is the basic device used in a Shift register? 4. What is the of Shift registers? 5. Give one application of shift register 6. What is SISO shift register. What is the IC used for it? 7. What is a Ring Counter? 8. What is a Bi-directional Shift register? 9. What is a PISO shift register? 10. Which is faster? ResearchGate has not been able to resolve any references for this publication. Anna University.

Regulation - 2013 Read more Discover more Download citation What type of file do you want. RIS BibTeX Plain Text What do you want to download. Citation only Citation and abstract Download ResearchGate iOS App Get it from the App Store now. Install Keep up with your stats and more Access scientific knowledge from anywhere or Discover by subject area Recruit researchers Join for free Login Email Tip: Most researchers use their institutional email address as their ResearchGate login Password Forgot password. Keep me logged in Log in or Continue with LinkedIn Continue with Google Welcome back. Keep me logged in Log in or Continue with LinkedIn Continue with Google No account. All rights reserved. Terms Privacy Copyright Imprint. I got to learn many new and interesting things in this college. This college served us with all round growth and learning with many courses, programs, fest organizations, etc. I got complete support from my college whenever needed in any difficulties. The college has greenery environment which makes you very comfortable and fresh. My branch was Mechanical. Practicals are very important with Theory lectures. All practical equipments are available in college. So it was easily understandable to me. The College has well equipped library and it also provides online study materials and mock tests for competitive exams.Different Technical Workshops, Industrial Visit and Placement Trainings are conducted in every year in College. All Sports and Culture Activities are conducted in College which are very enjoyable and entertaining. It was a great experience and I am happy to be part of it.” I feel every student has ability to succeed but quality guidance and supportive environment is required to achieve high level goals. At TPCT’s COE Osmanabad, all professors help you to discover your hidden talent and success quotient to achieve your ultimate goals.

In TPCT’s COE,there are knowledgeable teachers and college have good infrastructure, library,grounds,environment and I am happy to be part of it.” I have received more than enough support, technical knowledge, Skills which still encouraging me and I’m glad that I made the choice to choose TPCT’S College of Engineering to study my degree and P.G in Mechanical Engineering. I have gone from having zero confidence in myself to being so proud of what I have achieved in such a short time with the support of all professors and our expertise guides. This college is one who always thinks student benefit first.Osmanabad Pincode:- 413501. So this website was intended for free download articles fromYou are self-liable for your download.You can learn how to disable cookie here. Many types of counter circuits are available as digital building blocks, for example a number of chips in the 4000 series implement different counters. Occasionally there are advantages to using a counting sequence other than the natural binary sequence such as the binary coded decimal counter, a linear feedback shift register counter, or a Gray-code counter. Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.Note that each flip-flop has an asynchronous Reset (R’) input besides the synchronous J-K inputs. The asynchronous R’ input will be utilised in this experiment to initialise the flip-flop outputs as well as to obtain counters having cycle length N is less than 16.This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock.

If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), you will get another 1 bit counter that counts half as fast. Putting them together yields a two-bit counter:For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on. Synchronous counters can also be implemented with hardware finite state machines, which are more complex but allow for smoother, more stable transitions. Hardware-based counters are of this type.A decade counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the 7490 integrated circuit did) or other binary encodings (such as the bi-quinary encoding of the 7490 integrated circuit). The latter type of circuit finds applications in multiplexers and demultiplexers, or wherever a scanning type of behavior is useful. Similar counters with different numbers of outputs are also common. The decade counter is also known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). A Mod Counter that counts to 64 stops at 63 because 0 counts as a valid digit. This forces the counter to go to the state 0000 as soon as the counter makes the transition from the state 1001 representing count 9 to the next state 1010 according to the normal up counting sequence. In other words, changes in the output occur in “synchronisation” with the clock signal. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal, advancing one state for each pulse. These additional AND gates generate the required logic for the JK inputs of the next stage. Therefore, this type of counter is also known as a 4-bit Synchronous Up Counter. Here the counter starts with all of its outputs HIGH ( 1111 ) and it counts down on the application of each clock pulse to zero, ( 0000 ) before repeating again.

All we need to increase the MOD count of an up or down synchronous counter is an additional flip-flop and AND gate across it. After reaching the count of “1001”, the counter recycles back to “0000”. We now have a decade or Modulo-10 counter. Flip-flop FF0 toggles on every clock pulse. Thus, the count is reset and starts over again at “0000” producing a synchronous decade counter. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays. Please fill all fields. A:Design and implement a mod-4 up-down counter using D-flip flops. Note that a separate control is used to enable Up or Down operations. In need of ur help. In order to receive the past output some kind The memory element commonly used in the sequential The block diagram of the sequential circuit- Two such circuits areSome of theIf J and K are both high at the clock edge then the output will toggle from one state to the other.One can easily build any register or counterBut the clock input is under development, so it is not It produces the stored information on its output also in serial form. The block diagram is- The block diagram is- The block diagram is- The block diagram is- The sequence of states may follow the binary number sequence or an arbitrary manner (no sequence). The simplest example of a counter is the binary counter which follows the binary number sequence. An n-bit binary counter contains n flip-flops and can count binary numbers from 0 to (2n -1)(up counter which is incremental, if it counts decrementally it is then down counter).The data pattern contained within the shift register will recirculate as long as clock pulses are applied.Recirculating a single 1 around a ring counter divides the input clock by a factor equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the number of stages.To what state does the counter go on the next clock pulse?

What are the Q outputs after two clock pulses?The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, what the shift register will be storing?What will the count be after 31 clock pulses?The pin configuration is shown whenever the mouse is hovered on any canned component of the palette or press the 'show pinconfig' button. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. Accomplishment of each stage can be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module, secondly, on the module designed by the student, having gone through the theory, objective and procuder. By performing the experiment on the working module, students can only observe the input-output behavior. Where as, performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the input-output behavior. It is recommended to perform the experiments following the given guideline to check behavior and test plans along with their own circuit analysis. Then students are recommended to move on to the advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their knowledge base by further reading the references provided for the experiment.Try to use minimum number of components to build.The pin configuration of the canned components are shown when mouse hovered over a component or by using 'show pinconfig'button.

For more detail please refer to the manual for using the simulatorClock period can be set from the given 'set clock' button in the left toolbarThen there is no need to again press the 'simulate' button The pin configuration is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. According to the circuit diagram(given in the theory) connect all the components, connect 4 bit switches to the pin-8 of 4 D flipflop, connect a bit switch to the pin-5 of the left most D flipflop, connect 4 bit displayes to the pin-4 of 4 D flipflops. The pin configuration is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. According to the circuit diagram connect all the components, connect 4 bit switches to the pin-8 of 4 D flipflop, connect a bit switch to the pin-5 of the left most D flipflop, connect 4 bit displayes to the pin-4 of 4 D flipflops.New Age Publishers. Cambridge University Press Lab Senior Project Assistant The primary needThis pallete contains all the components and tools. Tools are used to act up on the components. Different tools:The area under every drawer is scrallable, if you are unable to see all the components in a particular drawer just click on the area and scroll. Different drawers: Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. After the connection is over click the selection tool in the pallete. Open and Save options are under development. Pin configurations of all the components- A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set. These are tag bits. These are data bits. These are output data bits and will be given only when there is a hit.

It consists of domain dependent simulation programs, experimental units called objects that encompass data files, tools that operate on these objects. The primary needExpert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment. By itself, it is simply a framework and a set of services for building a Eclipse comes with a standard set of plug-ins, including the Java Development Tools (JDT). The Graphical Editing Framework (GEF) allows developers to take an existing application model and quickly create a rich graphical editor. Licensing Terms. Combinational logic Gates, encoders,The outcome of sequential logic depends notExamples of sequential circuits are flip-flops,They are the basis for memory devices,Flip-flops may function in a number of ways and are thus classified accordinglyThe bar over the S should be treatedThis notation is used to indicate a signal that is active-LO. Its purpose is to indicate that the associated input or output is an active-LO signal. The output of the flip-flop will change only on the transition of the clock. Some flip-flops will change on the rising edge of the clock while others will change on the the falling edge. It is important to note theSpecial attention must be given to the timing diagram and data sheets. As one might expect, there is an area of uncertainty during which time the D-input mustAfter the rising edge ofAgain, the manufacturer will quote a maximumSee 74LS74 Data Sheet. In this particular case, data is transferred on the rising edge of the clock whileSee 74LS76 Data Sheet. Here are various things that flip-flops are used for. In (a), the flip-flop's clock input is edge sensitive. That is, the flip-flop changes state on one of the transitions of the clock. In (b), the flip-flop's set and clearThat is, the flip-flop remains in the set or cleared state as long as the set or clearIt is common for both modes to be used together in the design.

This is a hardware indicator or reminderIn these circumstances it is useful to consider the flip-flops together as a single time-state machine. In other words, firstly identify all the possible states required by the circuit and then, by design, incorporateA single T-type flip-flopIn other words,If you compare the input clockThe propagation delay between the input clock and when the last stageThus, all stages do not change at the same time. For this reasonSynchronous counters mayTheir characteristics, features, differences and modes. Discover everything Scribd has to offer, including books and audiobooks from major publishers. Start Free Trial Cancel anytime. Report this Document Download Now save Save lab experiment Design of Asynchronous and Synchro. For Later 6K views 2 2 upvotes 2 2 downvotes lab experiment Design of Asynchronous and Synchronous Counter Uploaded by Mani Bharathi Description: complete circuit Full description save Save lab experiment Design of Asynchronous and Synchro. For Later 2 2 upvotes, Mark this document as useful 2 2 downvotes, Mark this document as not useful Embed Share Print Download Now Jump to Page You are on page 1 of 6 Search inside document Browse Books Site Directory Site Language: English Change Language English Change Language. It may have been moved, or removed altogether. Perhaps you can return back to the site’s homepage and see if you can find what you are looking for. Tuttavia, alcune funzionalita del sito potrebbero essere disattivate. Per informazioni sull'eliminazione dei cookie, consultare la guida del browser in uso. Advertising: Consente ti connetterti ai social Advertising: Identifica il dispositivo in utilizzo Advertising: Raccoglie informazioni personali come il nome e la localita Advertising: Consente ti connetterti ai social Advertising: Identifica il dispositivo in utilizzo Advertising: Raccoglie informazioni personali come il nome e la localita. Please try again later.

Our payment security system encrypts your information during transmission. We don’t share your credit card details with third-party sellers, and we don’t sell your information to others. Please try again.Monday, Aug 17Monday, Aug 17No customer signatures are required at the time of delivery. To pay by cash, place cash on top of the delivery box and step back. Order delivery tracking to your doorstep is available.Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW.It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP).Flat 3% BACK for non-Prime members. Instant credit upto ?20,000. Check eligibility here. Here's how Avail EMI on Debit Cards. Get credit up to ?1,00,000. Check eligibility here Here's how Get GST invoice and save up to 28% on business purchases. Sign up for free Here's how Get daily rewards up to ?100 on shopping with Amazon Pay UPI. Check your eligibility here Here's how The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET).

A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). Count Maximum: 15; No.Amazon calculates a product's star ratings based on a machine learned model instead of a raw data average. The model takes into account factors including the age of a rating, whether the ratings are from verified purchasers and factors that establish reviewer trustworthiness. Please enable to view full site. Learn more about our privacy policy. For each clock tick, the 4-bit output increments by one. Each probe measures one bit of the output, with PR1 measuring the least significant bit and PR4 measuring the most significant bit. PR5 is the clock. Expand this circuit by adding a digital to analog converter! I tried designing my own first. This causes a fatal SIM error. What I can't find is any discussion of drawing these circuits with ground symbols, like in Multisim. How do I instruct students to simply not connect pins with GND symbols in MultisimLive when we explicitly do this in Multisim. Just a question for experts? This action cannot be undone.